The most important step in the fabrication of a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is the formation of buried layers for a collector region, which are capable of reducing the current amplification coefficient of a parasitic transistor consisted of a base region, the collector region and a substrate and thus to lower the saturation voltage drop of the device. The formation of the buried layers is not necessary for a high-speed SiGe HBT which has a heavily doped collector region, whilst it is required as necessary for a high-voltage SiGe HBT which has a lightly doped collector region.
Referring to FIG. 1 which illustrates a structure of a SiGe HBT of the prior art. The structure is as follows: two trenches 12 are formed in a substrate 11 and each trench is filled with a dielectric material which serves as an isolation structure; two pseudo buried layers 13 are formed under the respective trenches 12; a collector region 14 is formed in the portion of the substrate 11 between the two trenches 12 and the two pseudo buried layers 13; first dielectric portions 15 and a T-shaped SiGe base region 16 are formed above the collector region 14, and the first dielectric portions 15 are respectively located under two extending portions of the T-shaped SiGe base region 16; a sidewall 19b is formed above each of the isolation structure, on each outer side of the first dielectric portions 15 and the T-shaped SiGe base region 16; second dielectric portions 17 and a T-shaped polysilicon emitter 18 are formed on the SiGe base region 16, and the second dielectric portions 17 are located under two extending portions of the T-shaped polysilicon emitter 18, respectively; a sidewall 19a is formed above the T-shaped SiGe base region 16, on each outer side of the second dielectric portions 17 and the T-shaped polysilicon emitter 18; a third dielectric (also referred to as an interlayer dielectric) 113 is formed on the surface of the substrate, and a first hole 110, second holes 111 and third holes 112, each being filled with a metal electrode, are formed in the third dielectric layer; the emitter 18 is in contact with the electrode within the first hole 110; the SiGe base region 16 is in contact with electrodes within the second holes 111; and the pseudo buried layers 13 are in contact with the electrodes within the third holes 112.
In the above SiGe HBT, the cross section of each trench 12 has an inverted trapezoidal shape, i.e., the width of each trench 12 at its top is greater than that at its bottom. The trenches 12 with such a cross sectional shape can result in a good filling shape of a dielectric material and can achieve the improvement of rounding phenomena at its upper corners.
A method of manufacturing the SiGe HBT shown in FIG. 1 includes the following steps:
etching a substrate 11 to form two inverted-trapezoid-shaped trenches 12 by, for example, a shallow trench isolation (STI) process;
forming inner sidewalls in the trenches 12 and forming a pseudo buried layer 13 under the bottom of each trench 12 by using an ion implantation process, and removing the inner sidewalls in the trenches;
filling the trenches 12 with a dielectric material;
forming a collector region 14 in the portion of the substrate 11 between the two trenches 12 by using an ion implantation process;
depositing a first dielectric layer 15 and forming a base window therein, and epitaxially growing a SiGe material and forming a T-shaped poly SiGe base region 16 by using an etching process;
depositing a second dielectric layer 17 and forming an emitter window therein, and depositing a polysilicon material and forming a T-shaped polysilicon emitter 18 by using an etching process;
depositing a dielectric material 19 and forming emitter-region sidewalls 19a and base-region sidewalls 19b by using a dry etching process;
depositing a third dielectric layer (namely, the interlayer dielectric) 113, and etching it to form a first hole 110, second holes 111 and third holes 112 and making them contact with the T-shaped polysilicon emitter 18, the T-shaped poly SiGe base region 16 and the pseudo buried layers 13, respectively.
As each trench 12 has an inverted-trapezoidal-shaped cross section and the inner sidewalls formed in it are relatively thin, the energy of the implantation process for forming the pseudo buried layers 13 is greatly limited. In order to prevent ions from being implanted to penetrate the inner sidewalls of the trenches 12 and thus reach any of its inner side faces, a low-energy implantation process must be adopted, which can hardly meet the demand for a relatively high energy implantation to form pseudo buried layers 13 for a high-voltage SiGe HBT and thus will affect performance of the device.
As a low-energy ion implantation process is adopted to form the pseudo buried layers 13, it is difficult to achieve a lateral connection between the pseudo buried layers 13 within the active region through lateral diffusion. Moreover, it is impractical to adopt an annealing process to realize the lateral connection between the pseudo buried layers 13, as the annealing process will also cause the pseudo buried layers 13 to diffuse toward the surface of the collector region 14 and thus will affect the performance of the device.